In the field of digital logic, extensive use is made of well known and highly developed CMOS (complimentary metal-oxide semiconductor) technology. As CMOS has begun to approach maturity as a technology, there is an interest in alternatives that may lead to higher performance in terms of speed, power dissipation computational density, interconnect bandwidth, and the like. An alternative to CMOS technology comprises superconductor based single flux quantum circuitry, utilizing superconducting Josephson junctions, with typical signal power of around 4 nW (nanowatts), at a typical data rate of 20 Gb/s (gigabytes/second), or greater, and operating temperatures of around 4° Kelvin.
For decades, state-of-art for superconductor integrated circuits (ICs) typically had four metal layers, with either the top or bottom layers (or both) serving as a dedicated ground plane. In this geometry the ground return current flows below (or above) the signal wireup. More recently, state-of-art has moved to a larger number of metal layers, with sub-micrometer feature size with planarization. The concept of ground return above or below the signal trace in dedicated ground layers has been preserved. The problem is that as superconductor ICs scale to many metal layers at sub-micrometer feature size, the inductance of the lines using ground return paths above and/or below tends to be too large, as does cross-coupling between adjacent lines. Use of intermediate ground planes can alleviate this problem but is inefficient, as these ground planes reduce the number of metal layers available for wireup. Additionally, these intermediate ground planes need to be penetrated with through vias, and need to also have ground vias to provide a ground return path in the vertical dimension.